Size reduction of metal-oxide-semiconductor field-effect transistors (MOSFETs) has enabled continued improvement in speed, performance, density, and cost per unit function of integrated circuits. One way to further improve MOSFET performance is through selective application of stress to the transistor channel region. Stress distorts (i.e., strains) the semiconductor crystal lattice, and the distortion, in turn, affects the band alignment and charge transport properties of the semiconductor. By controlling the magnitude and distribution of stress in a finished device, carrier mobility can be increased and this improves device performance.
One approach of introducing stress in the transistor channel region includes growing an epitaxial layer of SiGe within recesses in the source/drain regions. In this approach, lattice mismatch between the epitaxial SiGe and the silicon substrate is used to create a uni-axial compressive stress within the channel region. This occurs because the SiGe lattice constant is greater than the underlying substrate lattice constant. One problem facing complementary metal-oxide-semiconductor (CMOS) manufacturing is that N-channel metal-oxide-semiconductor (NMOS) and P-channel metal-oxide-semiconductor (PMOS) devices require different types of stress in order to achieve increased carrier mobility. PMOS fabrication methods may include applying a compressive stress to the channel. However, the same compressive stress that benefits carrier mobility in PMOS devices is also detrimental to NMOS devices, which require a different stress, (e.g., Tensile stress), to increase carrier mobility. Therefore, CMOS manufacturing techniques may address PMOS and NMOS devices separately.
High germanium concentration in epitaxial silicon germanium (e-SiGe) may be needed to effectively boost channel compressive strain in PMOS devices. Boron dopant atoms may be incorporated into the e-SiGe to provide the required semiconductor doping to form the P-type transistor, and to lower sheet resistance and thus improve contact resistance in the SiGe source drain regions. However, because of the high concentration of boron in the e-SiGe, the boron may tend to out-diffuse into the transistor channel region. Boron out-diffusion in a PMOS may result in a voltage threshold (vt) reduction in short channel transistors. This roll-off in vt is referred to as a short channel effect (SCE). SCE is more predominant as transistor sizes are reduced in advanced semiconductor processes, and negatively impacts transistor performance. Control of the boron in the SiGe source/drain regions is therefore needed. As the source/drain regions are formed physically proximate to the channel region in order to provide the compressive stress needed boron atoms may diffuse into the channel region. The presence of unwanted boron in the channel region adversely impacts transistor performance.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the preferred embodiments and are not necessarily drawn to scale.